In manufacturing semiconductor devices, it is important that the devices are free of defects at the time of production, and reliable throughout their use. When defects are found in a die on a wafer, the percentage of usable die decreases, and the profitability of the manufacturer is impacted. More importantly, when a completed semiconductor device fails after it has been installed in a finished product, such as a consumer electronics product, the failure of the semiconductor device could cause the entire product to fail. That is, the failure of a single semiconductor device could render an entire consumer electronics device unusable. Accordingly, it is important that manufacturers of semiconductor devices identify and eliminate defects whenever possible.
When a semiconductor device is manufactured, a wafer receives a number of doping, layering, and patterning steps. Each of these steps must meet exacting physical requirements. For example, each layer is patterned to add or remove selected portions to form circuit features that will eventually make up a complete integrated circuit. The patterning process, such as photolithography, defines the dimensions of the circuit features. Problems encountered in the formation of any one layer could render an entire die unusable. Defective semiconductor devices are therefore tested in order to identify defective layers.
Once detected, these defective layers are analyzed in a process called failure analysis. During failure analysis, valuable information regarding problems with fabrication materials, process recipes, ambient air, personnel, process machines, and process materials could be discovered. Therefore, the detection of defects in a layer of an integrated circuit is critical to high yields and process control. When a new manufacturing process is being developed, a test structure for identifying defects in a layer could be specifically incorporated in the circuit for testing the new manufacturing process.
Identifying a specific defect in a defective layer requires an inspection of the structure by the user. Visual inspection is a common method of determining the failure in the integrated circuit. However, a visual inspection is a tedious process, requiring considerable time of an experienced engineer. Further, not all visual defects result in electrical failures. Therefore, to more closely analyze the visual defects, the engineer must typically perform both optical and scanning electron microscope (SEM) examinations. Also, many defects are not visible by initial inspection, thereby making the identification of the defects with a SEM difficult.
Accordingly, circuits have been developed to detect defective conductors. One example of a conventional circuit 100 for detecting a defective conductor is shown is shown in FIG. 1. In particular, a plurality of conductors 102A-102F comprise metal layers formed on the substrate of the integrated circuit. The conductors 102A-102F could comprise test conductors formed on the substrate in order to detect open circuits in conductors of interconnection layers. Although the conductors are formed on the surface of the substrate, some portions 103 of the conductors could extend into a diffusion region of the substrate, where the diffusion region provides a portion of the conductor. For example, a portion of the conductor may terminate at a diffusion region, and the conductor continues from another point of the diffusion region.
The circuit 100 of FIG. 1 enables the detection of the location of the defective conductor by providing a switching network to opposite ends of the conductors 102A-102F. In particular, a first switching network 104A comprising a plurality transistors 106A-106F is coupled to a first end of the conductors. The switching network 104A couples an input signal in_v to a conductor by way of one of the transistors. A second switching network 104B at a second end of the conductors enables the selection of a conductor. The output out_v of the second switching network 104B is coupled to a detection circuit 105, which outputs an output test signal indicating whether a conductor is defective.
Similarly, another switching network comprises a third switching network 110A having a plurality of transistors 112A-112F and a fourth switching network 110B having a plurality of transistors 114A-114F. A second input signal in_h is coupled from the third switching network to the fourth switching network by way of a second plurality of conductors 116A-116F. The output out_h of the fourth switching network 110B is also coupled to a detection circuit 118, which indicates whether a horizontal conductor is defective. Additional information related to conventional circuits for detecting defects in conductors formed on the substrate could be found in U.S. Pat. No. 6,509,739, issued to Voogel et al. on Jan. 21, 2003.
However, a defect could exist in a component formed in a substrate of an integrated circuit, such as a defect in a transistor. While significant efforts have been made to identify defective layers of an integrated circuit, conventional methods fail to detect a defect in a component formed in a substrate, and in particular identify the location of a defective component after the steps used to form an integrated circuit. Accordingly, there is a need for a circuit for and method of detecting a defect in a component formed in a substrate of an integrated circuit.